Testing an operation of integrated circuitry is challenging, because values (e.g., zero logic state “0,” one logic state “1” or high impedance state “Z”) of the integrated circuitry's internal nodes are difficult to observe. Nevertheless, in very large scale integration (“VLSI”) designs of integrated circuitry, such testing is important for identifying defects. Examples are: (a) logical built-in self-tests (“LBISTs”); (b) array built-in self-tests (“ABISTs”); and (c) more complicated tests with design-for-test (“DFT”) patterns, which specify various sequences of values to extensively check for possible defects in the integrated circuitry.
The DFT patterns themselves are complex and potentially error-prone. Accordingly, the DFT patterns themselves are subject to validation and debugging, in order to determine their suitability for use in such testing. In one example: (a) the DFT patterns are coded in a C programming language; (b) the integrated circuitry is placed into a board (e.g., AWANNG board or ET4×4 board); (c) the board executes the C program's encoded DFT patterns; and (d) in response to such execution, the board drives values of various inputs (e.g., C4 inputs and/or internal nodes) of the integrated circuitry and reads the resulting values of various outputs (e.g., C4 outputs and/or internal nodes) of the integrated circuitry.
In that manner, the board emulates a hardware environment of the integrated circuitry's operation in response to the DFT patterns. However, in such emulation, the board frequently interrupts its execution of the DFT patterns (e.g., after each simulation cycle), in order to: (a) drive values of the various inputs; and (b) measure resulting values of the various outputs. With such frequent interruptions, a speed and efficiency of such testing is significantly reduced, especially if the board executes the DFT patterns during millions of simulation cycles, and especially if some of the DFT patterns are incompletely validated and/or incompletely debugged before such testing.
Nevertheless, a need has arisen for a design structure for testing an operation of integrated circuitry, in which various shortcomings of previous techniques are overcome. For example, a need has arisen for a design structure for testing an operation of integrated circuitry, in which an operation of integrated circuitry is tested with higher speed and higher efficiency.